Wafer Testing & R/D Building, Powerchip Semiconductor Corp.

The project is located in the phase I development site leased by Powerchip Semiconductor Corp. The company established this Research & Testing Center to provide research, testing and office spaces to nearly 600 workers.
 
The above-grade levels are planned as the reception zone, a staff dining area, offices, research and testing center, production and other auxiliary spaces. The basement is mainly used as parking for cars and motorcycles, an air raid shelter and utility room. The garage has 326 spaces for cars and 253 for motorcycles.
 
The front façade features a creative, simple “frame” image to reflect the plan functions and cost effectiveness. The north-eastern side bordering the 8m main road and the spaces above the front entrance are the office area. Large curtain wall system is adopted on this side. The rest is the production section, using more economical composite boards. The anti-aging silver gray is the base color for the mass framed with champagne gold. The entrance canopy utilizes the corporate green to enhance the business image. The overall design expresses a unifying concept of high tech, high efficiency, economy, humanities and environmental friendliness.

Location: Hsinchu Science Park

Structural system: Steel, RC

Site area: 13,600 ㎡

Building coverage : 6,126 ㎡

Total floor area: 57,082 ㎡

No. of stories : 3 below, 6 above grade

Design period: 2007.03 ~ 2007.05

Const. period : 2007. 07 ~ 2008. 06

類別: Manufacturing、R&D

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